The cad/opensta port
opensta-2.2.0p0 – Parallax Static Timing Analyzer
Description
OpenSTA is a gate level static timing verifier. As a stand-alone
executable it can be used to verify the timing of a design using
standard file formats:
- Verilog netlist
- Liberty library
- SDC timing constraints
- SDF delay annotation
- SPEF parasitics
OpenSTA uses a TCL command interpreter to read the design, specify
timing constraints and print timing reports.
WWW: https://theopenroadproject.org/
- Only for arches
-
aarch64
aarch64
alpha
amd64
amd64
arm
arm
hppa
i386
i386
mips64
mips64
mips64el
mips64el
powerpc
powerpc
powerpc64
powerpc64
riscv64
riscv64
sparc64
- Categories:
-
cad
lang/tcl
Library dependencies
Build dependencies
Run dependencies